forth-riscv

My forth
git clone git://git.electrosoup.com/forth-riscv
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commit 1ca369a5a72b38003e932a2a6eb31a6f03a5f97f
parent 7b779979dd38e376675dd3971271f6c93e539c44
Author: Christian Ermann <christianermann@gmail.com>
Date:   Thu, 24 Oct 2024 18:20:53 -0700

Add 'emit' and 'key' to test input

Diffstat:
Mforth.s | 12++++++++++++
1 file changed, 12 insertions(+), 0 deletions(-)

diff --git a/forth.s b/forth.s @@ -97,9 +97,21 @@ defcode "type", 4, 0, type, exit jal uart_put_string next +defcode "emit", 4, 0, emit, type + pop a0 + jal uart_put_char + next + +defcode "key", 3, 0, key, emit + jal uart_get_char + push a0 + next + .section ".rodata" program: .int type + .int key + .int emit version_string: .ascii "soup forth rv32\n"