forth-riscv

My forth
git clone git://git.electrosoup.com/forth-riscv
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riscv32-virt.ld (857B)

      1 
      2 TARGET(binary)
      3 INPUT("src/bootstrap.fs")
      4 INPUT("src/tests.fs")
      5 
      6 OUTPUT_FORMAT("elf32-littleriscv", "elf32-littleriscv", "elf32-littleriscv")
      7 OUTPUT_ARCH(riscv)
      8 ENTRY(start)
      9 
     10 MEMORY {
     11     RAM (rwx) : ORIGIN = 0x80000000, LENGTH = 128M
     12 }
     13 
     14 SECTIONS {
     15     __stacksize = 256;
     16     __stacktop = ORIGIN(RAM) + LENGTH(RAM);
     17     __stacktop_ret = __stacktop - __stacksize;
     18     __stacktop_trap = __stacktop_ret - __stacksize;
     19     __stacktop_trap_ret = __stacktop_trap - __stacksize;
     20 
     21     . = ORIGIN(RAM);
     22     .text : { *(.text.boot); *(.text); *(.text.*) } >RAM
     23     .text : { __file_start = .; "src/bootstrap.fs" ; __file_end = .; } >RAM
     24     .rodata : { *(.rodata) } >RAM
     25     . = ALIGN(4);
     26     __here_start = .;
     27     __exec_start = . + 0x400;
     28     __code_start = . + 0x800;
     29     __meta_start = __here_start + 0x7000000;
     30 
     31     __sys_control = 0x100000;
     32 
     33     link_0 = 0;
     34 }
     35