forth-riscv

My forth
git clone git://git.electrosoup.com/forth-riscv
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ns16550a.s (1281B)

      1 .global uart_init
      2 .global uart_put_char
      3 .global uart_get_char
      4 .global uart_put_string
      5 
      6 .equ UART_ADDR, 0x10000000
      7 
      8 .equ INTERRUPT_ENABLE_REGISTER, 0x1
      9 .equ FIFO_CONTROL_REGISTER, 0x2
     10 .equ LINE_CONTROL_REGISTER, 0x3
     11 .equ LINE_STATUS_REGISTER, 0x5
     12 
     13 .equ LINE_STATUS_DATA_READY, 0x1
     14 .equ LINE_STATUS_TRANSMIT_EMPTY, 0x20
     15 
     16 .section ".text"
     17 
     18 uart_init:
     19     li   t0, UART_ADDR
     20     # Disable interrupts (for now)
     21     li   t1, 0x0
     22     sb   t1, INTERRUPT_ENABLE_REGISTER(t0)
     23     # 8 data bits, 1 stop bit, no parity
     24     li   t1, 0x3
     25     sb   t1, LINE_CONTROL_REGISTER(t0)
     26     # Enable FIFOs, clear rx and tx
     27     li   t1, 0x7
     28     sb   t1, FIFO_CONTROL_REGISTER(t0)
     29     ret
     30 
     31 uart_get_char:
     32     li   t0, UART_ADDR
     33 _wait_for_rx:
     34     lbu  t1, LINE_STATUS_REGISTER(t0)
     35     andi t1, t1, LINE_STATUS_DATA_READY
     36     beqz t1, _wait_for_rx
     37 _get_char:
     38     lbu  a0, (t0)
     39     ret
     40 
     41 uart_put_char:
     42     li   t0, UART_ADDR
     43 _wait_for_tx:
     44     lbu  t1, LINE_STATUS_REGISTER(t0)
     45     andi t1, t1, LINE_STATUS_TRANSMIT_EMPTY
     46     beqz t1, _wait_for_tx
     47 _put_char:
     48     sb   a0, (t0)
     49     ret
     50 
     51 uart_put_string:
     52 	addi s3, a0, 0
     53 	addi s4, a1, 0
     54 	addi s5, ra, 0
     55 	blez s4, _out_of_chars
     56 _next_char:
     57 	lb a0, 0(s3)
     58 	addi s3, s3, 1
     59 	addi s4, s4, -1
     60 	jal uart_put_char
     61 	bgtz s4, _next_char
     62 _out_of_chars:
     63 	addi ra, s5, 0
     64 	ret
     65